RISC OS Asm and BASIC Fun : DOCUMENTS
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Page last updated on Jan 12th of 2021.
Welcome:
This page will always be a work in progress, with more to come. That said it is just barely getting started at the moment.

Misc:
Just a little something to get a first document on the site, kind of small thing, though it is a document. More to come with time. One step at a time.

CPU Design:
This section is for notes on CPU design along with references where possible.
  • Some basic concepts.
  • Circuts Designs.
  • RISC Pipline basics.
  • Fan-in pipeline, or how to avoid bubles in the pipeline.
  • Fan-in with Pararllel execution, bring it to SuperScalar.
  • Data transfer, maximizing bus effeciency.
  • Atomic Instructions and locks.
  • Cache archetectures, many possibilities.
  • Improving Soft Inturrupt and Exception processing performance.
  • Harvard Archetecture vs Von-Neuman, and why either can be the best.
  • TLB implementation, and tree walking for page management.
  • A couple alternative MMU methods.
  • Minimizing issues of bus contention in multi master designs.
  • ...
While recently retyped, a lot of these notes have a bit of age to them.

I am still digging up references. Unfortunately there are a lot of sites that are off line and not archived, and it has only been a couple decades. Gos to show what we have said since 1992, you can not relly on ANY site withstanding the test of time. All sites are subject to disapearence, it is only a matter of when.