|Asm & Basic Fun : Assembly|
|This page is of first draft quality.
The sections of this page are:
Assembly Language is a human readable representation of the CPU's native instruction Opcodes (the Machine Language Opcodes of the CPU). Instructions in Assembly Language are represented in short easy to understand words, called mnemonics. Most mnemonics have parameters, to specify variants of instructions and different register usages. It is likely that, if you have not yet gotten to assembly language, it is a lot easier than you would expect.
There are many CPU's, each with its own Machine Language Opcodes, and with different Assembly Languages to represent the opcodes well. One of the easy to work with and fun to program for examples is the ARM series of CPU's. The ARM Instruction Set Archetecture (ISA) is a beautiful, simple, and Eloquent example. This is a very well designed ISA, that makes programming for it a true joy.
Many find writing Assembly Language on the ARM CPU to be very enjoyable. When you learn to code in assembly language, and learn to meditate through the troubles, it is very fun to write code in the CPU's terms. This lifts all restrictions on what can be done on each system, making anything possible, even those things that are not possible in a High Level Language.
RISC OS is very easy and fun to program for in Assembly Language. Using a software inturrupt with a comment field for making system calls, making it that much easier to code for in assembly language. RISC OS has many features that are unique, such as its form of module system, or the way the WIMP works, etc.
Many projects are said to be fast do to being written in assembly language, just think about that. Many are said to be small and fast, because they are written in assembly language. These statements are still made today about many projects that are written in assembly language, as unquestioned truths, what does that say.
|ARM Assembly on RISC OS:|
The ARM CPU is a well thought out RISC architecture CPU. Having a very eloquent and well thought out design of simplicity (Eloquence in the Mathematical sense). Many of the standard ALU instructions have the ability to shift the second input operand through a barrel shift, this does not add any time to execution and is completely free in terms of instructions and time. The only non-RISC instructions are the multiple load / store instructions that allow for many registers to be stored or loaded from memory in a single instruction. The ARM is a very easy CPU to program for in Assembly Language.
RISC OS is an ideal OS for programming in ARM Assembly Language, as the OS and ISA in many ways go together. Even the BBC BASIC V Interpreter, that is part of RISC OS, has a built in assembler. The SWI call primary API is as ARM in nature as you can get, taking advantage of a purely ARM feature for the better of the OS, Applications, and modules. RISC OS is so well suited to ARM assembly largely because it was originally written for the ARM, as the first widely distributed Operating System to run on the ARM CPU.
On RISC OS the ARM ISA is the 32-bit instruction ISA that has been around as long as the ARM CPU and RISC OS, with the extensions added up to ARMv7. Other ISA's such as THUMB, Jazzle, AARCH64, etc are NOT the ARM we look at, and are all more restricted in use than the ARM we know and use. Only the pure 32-bit Instruction word, with a native word size of 32 bits, nearly every opcode conditional, and free shifts on the standard data processing opcodes, is the ARM of RISC OS user programmers.
Some of modern RISC OS is losing its Assembly, as some are replacing the assembly with C. One of the best things about RISC OS is that it is mostly written in assembly. Thus it is up to RISC OS users to do what we can to revert our OS to the better language of ARM Assembly, and kick out C from the ROM. :) .
The following are parts of tutorials based on my relearning process on using ARM assembly in RISC OS. All of these are recent, and as such are a result of the work I am doing on understanding well what I used to do well with (before my stroke). These are likely to be slow to come. I will try to keep many of these in step with the equivlant in the BASIC section.
All of these tutorials are provided as dowinloads in ArcFS 2 Archives for use in RISC OS. The dowinloads have there source inside the Appicattion directory, in the subdirectory .src, thus far all the source code is provided as BASIC files that use the BASIC V assembler to assemble the source, this makes sure that everyone running RISC OS is able to assemble the source code.
That is for example the source for Wimp Assembly part 0 is in the BASIC (Type &FFB) file:
Have written a few more parts than available, I would like to get the BASIC versions equal to the Assembly Language Versions, if that takes too long I will just add the Assembly language versions anyway. Though you will note that I am better about releasing partial quality work (as in part zero where the documentation is not perfectly in sync with the code). A lot of partial quality work will be seen, I have given up on the perfectionist way I used to stick with.
|WDC65C816 Assembly on GS/OS:|
The WDC65C816 is a good CPU used in the Apple IIgs computer (and others). Being a 16-bit CPU able to run in 8-bit modes, and having a 24-bit address bus, this is a very capable CPU that is still quite usable to this day.
Assembly for GS/OS is fairly simple, with simple means of making System calls, and little to no restrictions on ability from the OS.
The 680x0 family implements what is likely the best of the CISC ISA's, at least in my opinion. This is also an ISA that will never die, as even today new Open Core implementations of the 680x0 continue to be made, with the Apollo 68080 being the current high end of this line.
The Assembly Language used to represent the 680x0 ISA is very easy to work with, though one must keep in mind that the destination parameter is on the right, the oposite of most other Assembly Languages.
This site created on RISC OS using !Zap.
It turns out to be easier to write and maintain a site with tables than one without tables.